Power semiconductor components which combine DMOS power transistors with large scale integrated logic impose particular demands on the metallization. To allow bonding to an active area, i.e. directly above the DMOS transistor cells, on the one hand a metal thickness of at least 3.0 μm is required. On the other hand, the logic metallization should be patterned as finely as possible in order to achieve a high packing density. However, this considerably limits the thickness of the metallization layer which can be used in the logic circuit structure.
With new power semiconductor circuit technologies, the problem is arising whereby the metal thicknesses which are required over the power DMOS transistor structure can no longer easily be patterned with the required fineness in the region of the logic circuit. In a modern power semiconductor technology, for example, a thickness of the power metallization of 3.5 μm and the following logic design rules are requirements: metal width: 1.6 μm; metal interconnect spacing: 1.6 μm and contact hole size: 1.2 μm. With a logic metallization thickness of 1.0 μm, these feature sizes can be produced without difficulties using current processes.
The problem of using finely patterned metal interconnects in the logic circuit structure to intelligently and inexpensively connect a thick power metallization has hitherto been solved by the circuitous route of a relatively expensive two-layer metallization. It is therefore desirable to simplify the metallization integration in order to reduce the process costs and enhance the competitiveness of modern technologies.
The present applicant has pursued the following solution approaches with a view to solving the problem described above in the technologies for the fabrication of integrated power semiconductor circuits:
I. In one technology for integrated power semiconductor circuits which is in production with the applicant, a 3.2 μm thick AlSiCu layer is sputtered on after the contact hole patterning and this layer is then patterned by plasma-chemical means using photoresist as a mask. This is followed by passivation and imide processing. The contact and metallization structures are relatively large, allowing this simple fabrication method which includes only one metallization level to be used.
II. Another technology which is in use with the present applicant for the fabrication of integrated power semiconductor circuits uses a significantly more complex two-layer metallization. After the contact hole patterning, a 1.0 μm thick AlSiCu layer is sputtered on and then once again patterned by plasma-chemical means using photoresist as a mask. Then, an oxide-nitride layer sequence is deposited and removed again above the DMOS surfaces and the contact-connection pads during the via etch. A further 2.5 μm thick AlSiCu layer is applied by sputtering and removed again using a photographic technique and a wet-chemical etch over the entirety of the logic surfaces apart from the logic contact-connection pads. As a result, a metallization thickness of 3.5 μm is achieved above the DMOS power transistor and in the contact-connection pads, whereas a passivated wiring with relatively small structures can be produced in the logic circuit. The metallization process is concluded by an imide processing operation.
In electrical terms, the intermetal dielectric is not required, since only a single metal level is used for wiring of the logic circuits. Consequently, the function of the intermetal dielectric is restricted to forming an etching stop for the wet-chemical power metal patterning and protecting the logic circuit metallization level below.
In view of the statements made above, it is an object of the present invention to provide an integrated semiconductor circuit of the type described in the introduction, as well as a method for fabricating it, which make it possible to realize an inexpensive and reliable logic and power metallization without the deposition and patterning of an intermetal dielectric for current and future integrated power semiconductor circuits.